公开(公告)号：US11694976B2

公开(公告)日：2023-07-04

申请号：US16158042

申请日：2018-10-11

Applicant: Intel Corporation

Inventor： Yuhong Cai ,  Sireesha Gogineni ,  Yi Xu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/03612 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/13026

Abstract: Embodiments described herein provide techniques for forming an interconnect structure that includes a bowl shaped pad. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a substrate (e.g., a semiconductor package, a PCB, etc.); and a metal pad over the substrate. The metal pad has a center region and an edge region. A thickness of the center region is smaller than a thickness of the edge region. A thickness of the center region may be non-uniform. The center region may have a bowl shape characterized by a stepped profile. The stepped profile is formed from metal layers arranged as steps. Alternatively, or additionally, the center region may have a bowl shape characterized by a curved profile. A pattern may be formed on or in a surface of the metal pad.

公开(公告)号：US11545464B2

公开(公告)日：2023-01-03

申请号：US16235859

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Yi Xu ,  Hyoung Il Kim ,  Florence Pon

IPC: H01L23/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.

公开(公告)号：US11211314B2

公开(公告)日：2021-12-28

申请号：US16633136

申请日：2017-09-21

Applicant: INTEL CORPORATION

Inventor： Hyoung Il Kim ,  Yi Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit structure may be fabricated having a first integrated circuit package comprising a first integrated circuit device electrically attached to a first surface of a first substrate, a second integrated circuit package comprising a second integrated circuit device electrically attached to a first surface of a second substrate and an opening extending between a first surface of the second substrate and the second surface of the second substrate, and an interconnection structure electrically attached to the first surface of the first substrate, wherein a portion of the interconnection structure extends into the second substrate opening and wherein the interconnection structure is electrically attached to a first surface of the second substrate.

公开(公告)号：US12237300B2

公开(公告)日：2025-02-25

申请号：US17113341

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Tyler Leuten ,  Yi Xu ,  Eleanor Patricia Paras Rabadam

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Integrated circuit assemblies may contain various mold, fill, and/or underfill materials. As these integrated circuit assemblies become ever smaller, it becomes challenging to prevent voids from forming within these materials, which may affect the reliability of the integrated circuit assemblies. Since integrated circuit assemblies are generally formed by electrically attaching integrated circuit dice on electronic substrates, the present description proposes injecting the mold, fill, and/or underfill materials through openings formed in the electronic substrate to fill voids that may form and/or to prevent the formation of the voids altogether.

公开(公告)号：US11848292B2

公开(公告)日：2023-12-19

申请号：US16158061

申请日：2018-10-11

Applicant: Intel Corporation

Inventor： Sireesha Gogineni ,  Yi Xu ,  Yuhong Cai

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/16227 ,  H01L2924/15323

Abstract: Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.

公开(公告)号：US11658079B2

公开(公告)日：2023-05-23

申请号：US16250683

申请日：2019-01-17

Applicant: Intel Corporation

Inventor： Hyoung Il Kim ,  Yi Xu ,  Florence Pon

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L2924/381

Abstract: Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.

公开(公告)号：US11948917B2

公开(公告)日：2024-04-02

申请号：US16392295

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Florence Pon ,  Yi Xu ,  James Zhang ,  Yuhong Cai ,  Tyler Leuten ,  William Glennan ,  Hyoung Il Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L25/50 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.

公开(公告)号：US11894334B2

公开(公告)日：2024-02-06

申请号：US16160212

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Yuhong Cai ,  Bilal Khalaf ,  Yi Xu

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/48 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/48011 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Embodiments disclosed herein include wire bonds and tools for forming wire bonds. In an embodiment, a wire bond may comprise a first attachment ball, and a first wire having a first portion contacting the first attachment ball and a second portion. In an embodiment, the wire bond may further comprise a second attachment ball, and a second wire having a first portion contacting the second attachment ball and a second portion. In an embodiment, the second portion of the first wire is connected to the second portion of the second wire.

公开(公告)号：US11652031B2

公开(公告)日：2023-05-16

申请号：US16219168

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Florence Pon ,  Yi Xu ,  Min-Tih Lai

IPC: H01L23/495 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L23/373 ,  H01L23/4985 ,  H01L23/49524 ,  H01L24/06 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate an elastomer coupled to the substrate and a plurality of bondfingers on the elastomer. The substrate, the elastomer and the bondfingers are configured to cooperatively expand and retract.

公开(公告)号：US20200312769A1

公开(公告)日：2020-10-01

申请号：US16365811

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Florence PON ,  Yi Xu

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to an interposer with step features used to electrically couple stacked dies. In embodiments, the step features may appear as a ziggurat shape to one or more sides of the interposer, which may be referred to as a ziggurat interposer. The interposer may have electrical routing disposed within to electrically couple the first face of the one of the step features with a die.