An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.