公开(公告)号：US10979353B2

公开(公告)日：2021-04-13

申请号：US15622936

申请日：2017-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/741 ,  H04L12/743

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

公开(公告)号：US10333847B2

公开(公告)日：2019-06-25

申请号：US15987041

申请日：2018-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743 ,  G06F9/38

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

公开(公告)号：US10104004B2

公开(公告)日：2018-10-16

申请号：US14072989

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/875 ,  H04L12/741 ,  H04L29/06 ,  H04L12/707

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

公开(公告)号：US20180270154A1

公开(公告)日：2018-09-20

申请号：US15987041

申请日：2018-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743 ,  G06F9/38

CPC classification number: H04L45/7453 ,  G06F9/3853 ,  H04L45/7457

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

公开(公告)号：US10009276B2

公开(公告)日：2018-06-26

申请号：US14190734

申请日：2014-02-26

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743 ,  G06F9/38

CPC classification number: H04L45/7453 ,  G06F9/3853 ,  H04L45/7457

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

公开(公告)号：US20160191373A1

公开(公告)日：2016-06-30

申请号：US15062245

申请日：2016-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart

IPC: H04L12/733 ,  H04L12/741

CPC classification number: H04L45/20 ,  H04L45/50 ,  H04L45/74

Abstract: A network switch includes a plurality of ports, a parser coupled to the plurality of ports, and a processor coupled to the ports and configured to process a received packet via one of the ports. The received packet includes a first header field, a second header field, and a destination header field, each of the first, second, and destination header fields including a TTL field. The parser is configured to decide a valid bit for each of the first header field, the second header field and the destination header field, based on an availability for each of the first header field, the second header field and the destination header field. The processor is configured to execute an instruction to cause content of a select one of the first or second header field's TTL field to be copied to the destination header field.

Abstract translation: 网络交换机包括多个端口，耦合到所述多个端口的解析器，以及耦合到所述端口并被配置为经由所述端口之一来处理接收的分组的处理器。 所接收的分组包括第一报头字段，第二报头字段和目的地报头字段，第一，第二和目的报头字段中的每一个包括TTL字段。 解析器被配置为基于第一报头字段，第二报头字段和目的地报头字段中的每一个的可用性来决定第一报头字段，第二报头字段和目的地报头字段中的每一个的有效位。 处理器被配置为执行使第一或第二报头字段的TTL字段中的选择的一个的内容被复制到目的地报头字段的指令。

公开(公告)号：US09313127B2

公开(公告)日：2016-04-12

申请号：US14025177

申请日：2013-09-12

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart

IPC: H04J3/00 ,  H04L12/56 ,  H04L29/12

CPC classification number: H04L45/741 ,  H04L61/251 ,  H04L61/6004 ,  H04L61/6095

Abstract: In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.

Abstract translation: 在本发明的实施例中，讨论了在计算机硬件上执行字节旋转合并的方法。 在第一和第二源操作数上执行字节旋转，并分别由第一和第二旋转常数进行字节旋转。 第一个字节旋转输出和第二个字节旋转输出合并。 来自字节掩码的控制位是逻辑1时，来自第一个字节旋转输出的字节被输出到一个字节旋转合并输出。 来自字节掩码的控制位为逻辑0时，来自第二字节旋转输出的字节被输出到字节旋转合并输出。

公开(公告)号：US09258224B2

公开(公告)日：2016-02-09

申请号：US14190770

申请日：2014-02-26

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/741 ,  H04L12/935 ,  H04L12/743

CPC classification number: H04L45/745 ,  H04L45/74 ,  H04L45/7457 ,  H04L49/3063

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract translation: 本发明的实施例包括用于交换网络中的分组处理的存储器和装置。 存储器包括多个单词，其中每个单词包括多个位。 多个单词中的每个单词通过单独和不同的读取地址来寻址。 逻辑电路对由单独和不同读取地址寻址的所有单词中的所有位执行逻辑“或”功能，并输出结果。

公开(公告)号：US20150262668A1

公开(公告)日：2015-09-17

申请号：US14618057

申请日：2015-02-10

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of match entries. Each TCAM block is ranked in priority order. The TCAM also includes a group of TCAM headpointers. There is a TCAM headpointer coupled to each TCAM block. The TCAM headpointer indicates the highest priority match in the group of match entries in a TCAM block. The match entries within a TCAM block are prioritized in circular priority order starting from the highest priority match.

Abstract translation: 本发明的实施例包括包括一组TCAM块的三进制内容可寻址存储器（TCAM）。 每个TCAM块存储多个匹配条目。 每个TCAM块按优先顺序排列。 TCAM还包括一组TCAM头部指针。 有一个连接到每个TCAM块的TCAM头指针。 TCAM头指针指示TCAM块中的匹配项组中的最高优先级匹配。 TCAM块中的匹配条目以最高优先级匹配开始以循环优先级顺序进行优先级排序。

公开(公告)号：US20140241362A1

公开(公告)日：2014-08-28

申请号：US14193190

申请日：2014-02-28

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/761 ,  H04L29/06

CPC classification number: H04L69/22 ,  H04L45/00 ,  H04L45/74

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

Abstract translation: 一个数据包处理块。 该块具有用于在分组报头向量中接收数据的输入，该矢量包括表示分组的信息的数据和用于执行分组报头向量数据与至少一个匹配表之间的匹配操作的匹配单元。 各种实施例提供了在匹配表外部存储某些动作或下一个表位或表中的常数或通过从多个单元匹配表存储器形成匹配表的优点。