Invention Grant
- Patent Title: Gate aligned contact and method to fabricate same
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Application No.: US15624036Application Date: 2017-06-15
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Publication No.: US10340185B2Publication Date: 2019-07-02
- Inventor: Oleg Golonzka , Swaminathan Sivakumar , Charles H. Wallace , Tahir Ghani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/768 ; H01L21/306 ; H01L27/088 ; H01L29/66 ; H01L21/28 ; H01L21/8234 ; H01L27/02 ; H01L23/535 ; H01L29/06 ; H01L21/32

Abstract:
Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
Public/Granted literature
- US20170294350A1 GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME Public/Granted day:2017-10-12
Information query
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