- 专利标题: Clock data recovery in multilane data receiver
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申请号: US15802365申请日: 2017-11-02
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公开(公告)号: US10347283B2公开(公告)日: 2019-07-09
- 发明人: Ali Hormati , Armin Tajalli
- 申请人: KANDOU LABS, S.A.
- 申请人地址: CH Lausanne
- 专利权人: KANDOU LABS, S.A.
- 当前专利权人: KANDOU LABS, S.A.
- 当前专利权人地址: CH Lausanne
- 代理机构: Invention Mine LLC
- 主分类号: G11B20/10
- IPC分类号: G11B20/10 ; H04L7/033 ; H03L7/099 ; G06F15/82 ; H03L7/085 ; G06F13/40
摘要:
Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (i) a phase of one or more phases of a local oscillator signal and (ii) a corresponding data signal associated with one of the two or more data lanes, generating a composite phase-error signal representing a combination of the two or more obtained data-derived phase-error signals, receiving the composite phase-error signal at a loop filter responsively generating an oscillator control signal, and receiving the oscillator control signal at a local oscillator and responsively adjusting a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.
公开/授权文献
- US20190130942A1 CLOCK DATA RECOVERY IN MULTILANE DATA RECEIVER 公开/授权日:2019-05-02
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