公开(公告)号：US11804845B2

公开(公告)日：2023-10-31

申请号：US17689649

申请日：2022-03-08

申请人： KANDOU LABS, S.A.

发明人： Armin Tajalli ,  Ali Hormati

IPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/23 ,  H03L7/08 ,  H03L7/093

CPC分类号： H03L7/0816 ,  H03L7/081 ,  H03L7/0807 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0998 ,  H03L7/23 ,  H03L2207/06

摘要： Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.

公开(公告)号：US11784782B2

公开(公告)日：2023-10-10

申请号：US18158403

申请日：2023-01-23

申请人： Kandou Labs, S.A.

发明人： Roger Ulrich ,  Armin Tajalli ,  Ali Hormati ,  Richard Simpson

IPC分类号： H04L7/00 ,  H04L25/14 ,  H04L7/033 ,  H04L25/49 ,  H04L25/03

CPC分类号： H04L7/0016 ,  H04L7/0054 ,  H04L7/0079 ,  H04L7/033 ,  H04L25/03 ,  H04L25/03057 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4904 ,  H04L7/0025 ,  H04L25/03878 ,  H04L2025/03356

摘要： Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

公开(公告)号：US11716226B2

公开(公告)日：2023-08-01

申请号：US17700182

申请日：2022-03-21

申请人： Kandou Labs, S.A.

发明人： Roger Ulrich

IPC分类号： H04L25/03 ,  H04B3/04 ,  H03K19/0185 ,  H03K19/00 ,  H04L25/49

CPC分类号： H04L25/03878 ,  H03K19/0013 ,  H03K19/0185 ,  H04B3/04 ,  H04L25/03133 ,  H04L25/03343 ,  H04L25/4917

摘要： A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

公开(公告)号：US11677539B2

公开(公告)日：2023-06-13

申请号：US17840006

申请日：2022-06-14

申请人： Kandou Labs, S.A.

发明人： Armin Tajalli

IPC分类号： H04L7/033 ,  H03K19/21 ,  H03L7/08 ,  H03L7/085 ,  H03L7/099 ,  H04L7/00

CPC分类号： H04L7/0331 ,  H03K19/215 ,  H03L7/085 ,  H03L7/0807 ,  H03L7/099 ,  H04L7/0087 ,  H04L7/033

摘要： Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

公开(公告)号：US11632114B2

公开(公告)日：2023-04-18

申请号：US17666242

申请日：2022-02-07

申请人： Kandou Labs, S.A.

发明人： Armin Tajalli

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H04L7/033 ,  H04L25/14 ,  H04L25/02 ,  H04L25/40 ,  H04L25/493 ,  H03K19/21 ,  H03L7/089 ,  H04L7/00

摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

公开(公告)号：US20220286145A1

公开(公告)日：2022-09-08

申请号：US17746778

申请日：2022-05-17

申请人： Kandou Labs, S.A.

发明人： Amin Shokrollahi ,  Dario Carnelli

IPC分类号： H03M13/15 ,  H03M13/00 ,  H04L1/00 ,  H03M13/37 ,  H03M13/09

摘要： Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

公开(公告)号：US11240076B2

公开(公告)日：2022-02-01

申请号：US16449145

申请日：2019-06-21

申请人： Kandou Labs, S.A.

发明人： Amin Shokrollahi

IPC分类号： H04L25/49 ,  H04L1/00 ,  H04L25/02 ,  H04J13/12 ,  B41J2/00 ,  H03M5/14 ,  H04J13/16

摘要： Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

公开(公告)号：US11128129B2

公开(公告)日：2021-09-21

申请号：US16579518

申请日：2019-09-23

申请人： Kandou Labs, S.A.

发明人： Kiarash Gharibdoust ,  Suhas Rattan ,  Pallavi Muktesh

IPC分类号： H02H9/00 ,  H02H9/04

摘要： Methods and systems are described for selectively providing a signal path from a respective wire of a multi-wire bus to at least one corresponding data signal output node of at least one set of differential data signal output nodes using a respective switching element in a respective set of signal path circuits connected in parallel, and generating a set of discharge currents, each discharge current of the set of discharge currents generated through a respective resistive element in the respective set of signal path circuits to discharge a portion of a voltage pulse on the respective wire of the multi-wire bus to one or more metallic planes via a respective localized ESD protection circuit, the respective resistive element and the respective localized ESD protection circuit connected between the respective wire and the respective switching element.

公开(公告)号：US10742451B2

公开(公告)日：2020-08-11

申请号：US16435412

申请日：2019-06-07

申请人： Kandou Labs, S.A.

发明人： Armin Tajalli ,  Chen Cao ,  Kiarash Gharibdoust

IPC分类号： H04L25/02

摘要： Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

公开(公告)号：US10693473B2

公开(公告)日：2020-06-23

申请号：US15986582

申请日：2018-05-22

申请人： Kandou Labs, S.A.

发明人： Armin Tajalli ,  Ali Hormati

IPC分类号： H03L7/00 ,  H03L7/089 ,  H03L7/099 ,  H03L7/081 ,  H03L7/23 ,  H03L7/08 ,  H03L7/093

摘要： Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.