Invention Grant
- Patent Title: Wafer-scale integration of vacancy centers for spin qubits
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Application No.: US15928220Application Date: 2018-03-22
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Publication No.: US10347834B2Publication Date: 2019-07-09
- Inventor: Nicole K. Thomas , Marko Radosavljevic , Sansaptak Dasgupta , Ravi Pillarisetty , Kanwaljit Singh , Hubert C. George , Jeanette M. Roberts , David J. Michalak , Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , James S. Clarke
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: H01L49/00
- IPC: H01L49/00 ; G02B6/12 ; G06N10/00 ; B82Y10/00 ; B82Y40/00 ; B82Y20/00

Abstract:
Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.
Public/Granted literature
- US20190044066A1 WAFER-SCALE INTEGRATION OF VACANCY CENTERS FOR SPIN QUBITS Public/Granted day:2019-02-07
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