公开(公告)号：US12211841B2

公开(公告)日：2025-01-28

申请号：US18311582

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L27/088 ,  G06N10/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778 ,  H10N69/00 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US11990516B1

公开(公告)日：2024-05-21

申请号：US17480722

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Brennen Karl Mueller ,  James S. Clarke

IPC: H01L29/12 ,  G06N10/00 ,  H01L27/088 ,  H01L29/66 ,  H10N69/00

CPC classification number: H01L29/122 ,  G06N10/00 ,  H01L27/088 ,  H01L29/66977 ,  H10N69/00

Abstract: Quantum dot devices with independent gate control are disclosed. An example quantum dot device includes N parallel rows of gate lines provided over a quantum well stack. Each of the N parallel rows of gate lines defines a respective row of a quantum dot formation region in the quantum well stack and includes M parallel gate lines stacked above one another. The quantum dot device may further include, for each of the N×M gate lines, a gate that extends toward the quantum well stack, where, for an individual row of the N parallel rows, gates that extend toward the quantum well stack from the M parallel stacked gate lines are arranged above a respective row of a quantum dot formation region in the quantum well stack. In this manner, each of the N×M gates responsible for formation of different quantum dots may be controlled independently.

公开(公告)号：US11881432B2

公开(公告)日：2024-01-23

申请号：US18088474

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L21/76843 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2224/45015 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US11664446B2

公开(公告)日：2023-05-30

申请号：US17468090

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Hubert C. George ,  James S. Clarke

IPC: B82Y10/00 ,  H01L29/76 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7613 ,  H01L29/0665 ,  H01L29/4236 ,  H01L29/42356 ,  H01L29/66439 ,  B82Y10/00

Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.

公开(公告)号：US11569126B2

公开(公告)日：2023-01-31

申请号：US17061062

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US11450765B2

公开(公告)日：2022-09-20

申请号：US16143676

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/778 ,  H01L29/51 ,  H01L29/49 ,  H01L29/15 ,  H01L27/02 ,  H01L29/82 ,  H01L29/66 ,  H01L23/538 ,  G06N10/00

Abstract: A quantum dot device is disclosed that includes a fin and a gate above the fin. The fin may extend away from a base and include a quantum well stack in which one or more quantum dots may be formed during operation of the quantum dot device. The gate may include a gate electrode material having a first portion and a second portion, where the first portion is above the quantum well stack and the second portion is a portion that is not above the quantum well stack and is separated from the base by an insulating material. The quantum dot device may further include a metal structure between the second portion of the gate electrode material and the base, forming a portion of a diode provided in series with the gate, which diode may provide at least some ESD protection for the quantum dot device.

公开(公告)号：US20220140086A1

公开(公告)日：2022-05-05

申请号：US17578693

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/423 ,  H01L29/76 ,  H01L29/82 ,  H01L29/66 ,  H01L29/775

Abstract: Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.

公开(公告)号：US20220140085A1

公开(公告)日：2022-05-05

申请号：US17577515

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  James S. Clarke ,  Adel A. Elsherbini

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/423 ,  H01L23/538 ,  B82Y10/00 ,  H01L29/76 ,  H01L25/065 ,  H01L23/00 ,  H01L29/165 ,  H01L29/06

Abstract: Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate.

公开(公告)号：US11276756B2

公开(公告)日：2022-03-15

申请号：US16329710

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/423 ,  H01L29/76 ,  H01L29/82 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778

Abstract: Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.

公开(公告)号：US11183564B2

公开(公告)日：2021-11-23

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/165 ,  H01L27/18 ,  H01L21/8234 ,  H01L29/10 ,  G06N10/00 ,  H01L39/14 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/40 ,  H01L21/321 ,  H01L21/02 ,  H01L29/778 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.