公开(公告)号：US12211841B2

公开(公告)日：2025-01-28

申请号：US18311582

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L27/088 ,  G06N10/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778 ,  H10N69/00 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US20230073078A1

公开(公告)日：2023-03-09

申请号：US17445856

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Sudipto Naskar ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Marko Radosavljevic ,  Nicole K. Thomas ,  Patrick Morrow ,  Urusa Alaan

IPC: H01L27/12

Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

公开(公告)号：US11450765B2

公开(公告)日：2022-09-20

申请号：US16143676

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/778 ,  H01L29/51 ,  H01L29/49 ,  H01L29/15 ,  H01L27/02 ,  H01L29/82 ,  H01L29/66 ,  H01L23/538 ,  G06N10/00

Abstract: A quantum dot device is disclosed that includes a fin and a gate above the fin. The fin may extend away from a base and include a quantum well stack in which one or more quantum dots may be formed during operation of the quantum dot device. The gate may include a gate electrode material having a first portion and a second portion, where the first portion is above the quantum well stack and the second portion is a portion that is not above the quantum well stack and is separated from the base by an insulating material. The quantum dot device may further include a metal structure between the second portion of the gate electrode material and the base, forming a portion of a diode provided in series with the gate, which diode may provide at least some ESD protection for the quantum dot device.

公开(公告)号：US20220140086A1

公开(公告)日：2022-05-05

申请号：US17578693

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/423 ,  H01L29/76 ,  H01L29/82 ,  H01L29/66 ,  H01L29/775

Abstract: Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.

公开(公告)号：US20220140085A1

公开(公告)日：2022-05-05

申请号：US17577515

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  James S. Clarke ,  Adel A. Elsherbini

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/423 ,  H01L23/538 ,  B82Y10/00 ,  H01L29/76 ,  H01L25/065 ,  H01L23/00 ,  H01L29/165 ,  H01L29/06

Abstract: Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate.

公开(公告)号：US11276756B2

公开(公告)日：2022-03-15

申请号：US16329710

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/423 ,  H01L29/76 ,  H01L29/82 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778

Abstract: Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.

公开(公告)号：US11183564B2

公开(公告)日：2021-11-23

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/165 ,  H01L27/18 ,  H01L21/8234 ,  H01L29/10 ,  G06N10/00 ,  H01L39/14 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/40 ,  H01L21/321 ,  H01L21/02 ,  H01L29/778 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US11063040B2

公开(公告)日：2021-07-13

申请号：US16340512

申请日：2016-12-24

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L27/088 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/18 ,  H01L29/66 ,  H01L29/778 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US11011693B2

公开(公告)日：2021-05-18

申请号：US16450396

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Thomas Francis Watson ,  Stephanie A. Bojarski ,  James S. Clarke

IPC: H01L39/04 ,  H01L39/02 ,  H01L39/22 ,  G06N10/00 ,  H01L23/552 ,  H01L27/18 ,  H01L23/46

Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.

公开(公告)号：US20200373351A1

公开(公告)日：2020-11-26

申请号：US16635193

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Wesley T. Harrison ,  Adel A. Elsherbini ,  Stefano Pellerano ,  Zachary R. Yoscovits ,  Lester Lampert ,  Ravi Pillarisetty ,  Roman Caudillo ,  Hubert C. George ,  Nicole K. Thomas ,  David J. Michalak ,  Kanwaljit Singh ,  James S. Clarke

IPC: H01L27/18 ,  H01L39/02

Abstract: Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.