Invention Grant
- Patent Title: Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC
-
Application No.: US15786321Application Date: 2017-10-17
-
Publication No.: US10354733B1Publication Date: 2019-07-16
- Inventor: Jindrich Zejda , Elliott Delaye , Ashish Sirasao , Yongjun Wu , Aaron Ng
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Steven Roberts
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C16/10 ; G06N3/04 ; G06F12/06 ; G06F13/16 ; G06N20/00
Abstract:
Methods and apparatus are described for partitioning and reordering block-based matrix multiplications for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). By preloading and hierarchically caching the blocks, examples of the present disclosure reduce the double data rate (DDR) memory intake bandwidth for software-defined GEMM accelerators.
Information query
