Invention Grant
- Patent Title: Error handling in transactional buffered memory
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Application No.: US15462185Application Date: 2017-03-17
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Publication No.: US10360096B2Publication Date: 2019-07-23
- Inventor: Brian S. Morris , Bill Nale , Robert G. Blankenship , Eric L. Hendrickson
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/08 ; G06F11/16 ; G06F13/00 ; H04L1/00 ; H04L1/18

Abstract:
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.
Public/Granted literature
- US20170322841A1 ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY Public/Granted day:2017-11-09
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