Invention Grant
- Patent Title: Patterning method
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Application No.: US15641235Application Date: 2017-07-04
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Publication No.: US10361080B2Publication Date: 2019-07-23
- Inventor: Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Agent Winston Hsu
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/311 ; H01L21/033 ; H01L27/108 ; H01L21/3213

Abstract:
A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.
Public/Granted literature
- US20190013201A1 PATTERNING METHOD Public/Granted day:2019-01-10
Information query
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