Invention Grant
- Patent Title: Fabrication of vertical fin transistor with multiple threshold voltages
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Application No.: US15783693Application Date: 2017-10-13
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Publication No.: US10361301B2Publication Date: 2019-07-23
- Inventor: Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/66 ; H01L29/78 ; H01L27/088 ; H01L29/161 ; H01L29/165 ; H01L21/02 ; H01L21/762 ; H01L21/8234
Abstract:
A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
Public/Granted literature
- US20180053846A1 FABRICATION OF VERTICAL FIN TRANSISTOR WITH MULTIPLE THRESHOLD VOLTAGES Public/Granted day:2018-02-22
Information query
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