Invention Grant
- Patent Title: I/O writes with cache steering
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Application No.: US15826065Application Date: 2017-11-29
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Publication No.: US10366027B2Publication Date: 2019-07-30
- Inventor: Eric Christopher Morton , Elizabeth Cooper , William L. Walker , Douglas Benson Hunt , Richard Martin Born , Richard H. Lee , Paul C. Miranda , Philip Ng , Paul Moyer
- Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
- Applicant Address: US CA Santa Clara CA Markham
- Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee Address: US CA Santa Clara CA Markham
- Main IPC: G06F13/28
- IPC: G06F13/28 ; G06F12/0815 ; G06F12/0862 ; G06F12/0891 ; G06F12/0893

Abstract:
A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.
Public/Granted literature
- US20190163656A1 I/O WRITES WITH CACHE STEERING Public/Granted day:2019-05-30
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