公开(公告)号：US12124865B2

公开(公告)日：2024-10-22

申请号：US17219051

申请日：2021-03-31

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Sean T. White ,  Philip Ng

IPC: G06F9/455 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0882

CPC classification number: G06F9/45545 ,  G06F9/45558 ,  G06F12/063 ,  G06F12/0811 ,  G06F12/0882 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: Methods and apparatus for providing page migration of pages among tiered memories identify frequently accessed memory pages in each memory tier and generate page hotness ranking information indicating how frequently memory pages are being accessed. Methods and apparatus provide the page hotness ranking information to an operating system or hypervisor depending on which is used in the system, the operating system or hypervisor issues a page move command to a hardware data mover, based on the page hotness ranking information and the hardware data mover moves a memory page to a different memory tier in response to the page move command from the operating system.

公开(公告)号：US11860797B2

公开(公告)日：2024-01-02

申请号：US17565666

申请日：2021-12-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Philip Ng ,  Nippon Raval ,  David A. Kaplan ,  Donald P. Matthews, Jr.

IPC: G06F13/10 ,  G06F12/084 ,  G06F12/1081

CPC classification number: G06F13/102 ,  G06F12/084 ,  G06F12/1081 ,  G06F2212/603

Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.

公开(公告)号：US20220283946A1

公开(公告)日：2022-09-08

申请号：US17189844

申请日：2021-03-02

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Philip Ng ,  Nippon Raval ,  BuHeng Xu ,  Rostislav S. Dobrin ,  Shawn Han

IPC: G06F12/0831 ,  G06F12/02 ,  G06F12/1009 ,  G06F13/16 ,  G06F13/24

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.

公开(公告)号：US10223280B2

公开(公告)日：2019-03-05

申请号：US16025449

申请日：2018-07-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Vydhyanathan Kalyanasundharam ,  Yaniv Adiri ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien

IPC: G06F3/14 ,  G06F13/38 ,  G06F12/1009 ,  G06F12/12 ,  G06F12/1045

Abstract: A system including a gasket communicatively coupled between a unified northbridge (UNB) having a cache coherent interconnect (CCI) interface and a processor having an Advanced eXtensible Interface (AXI) coherency extension (ACE). The gasket is configured to translate requests from the processor that include ACE commands into equivalent CCI commands, wherein each request from the processor maps onto a specific CCI request type. The gasket is further configured to translate ACE tags into CCI tags. The gasket is further configured to translate CCI encoded probes from a system resource interface (SRI) into equivalent ACE snoop transactions. The gasket is further configured to translate the memory map to inter-operate with a UNB/coherent HyperTransport (cHT) environment. The gasket is further configured to receive a barrier transaction that is used to provide ordering for transactions.

公开(公告)号：US20180307619A1

公开(公告)日：2018-10-25

申请号：US16025449

申请日：2018-07-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien ,  Yaniv Adiri

IPC: G06F12/1009 ,  G06F12/1045 ,  G06F12/12

CPC classification number: G06F12/1009 ,  G06F12/1045 ,  G06F12/12 ,  G06F2212/684

Abstract: A system including a gasket communicatively coupled between a unified northbridge (UNB) having a cache coherent interconnect (CCI) interface and a processor having an Advanced eXtensible Interface (AXI) coherency extension (ACE). The gasket is configured to translate requests from the processor that include ACE commands into equivalent CCI commands, wherein each request from the processor maps onto a specific CCI request type. The gasket is further configured to translate ACE tags into CCI tags. The gasket is further configured to translate CCI encoded probes from a system resource interface (SRI) into equivalent ACE snoop transactions. The gasket is further configured to translate the memory map to inter-operate with a UNB/coherent HyperTransport (cHT) environment. The gasket is further configured to receive a barrier transaction that is used to provide ordering for transactions.

公开(公告)号：US10025721B2

公开(公告)日：2018-07-17

申请号：US14523705

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien ,  Yaniv Adiri

IPC: G06F12/10 ,  G06F12/12 ,  G06F12/1009 ,  G06F12/1045 ,  G06F13/38

Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

公开(公告)号：US09239804B2

公开(公告)日：2016-01-19

申请号：US14045701

申请日：2013-10-03

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew Kegel ,  Jimshed Mirza ,  Paul Blinzer ,  Philip Ng

IPC: G06F11/07 ,  G06F13/00 ,  G06F12/10 ,  G06F12/00 ,  G06F13/38

CPC classification number: G06F13/00 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0793 ,  G06F12/00 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1081 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (IOMMU) receives a peripheral page request (PPR) from a peripheral. In response to a determination that a criterion regarding an available capacity of a PPR log is satisfied, a completion message is sent to the peripheral indicating that the PPR is complete and the PPR is discarded without queuing the PPR in the PPR log.

Abstract translation: 提供了一种在计算机系统中管理来自外围设备的请求的系统和方法。 在系统和方法中，输入/输出存储器管理单元（IOMMU）从外设接收外围寻呼请求（PPR）。 响应于满足关于PPR日志的可用容量的标准的确定，向外设发送完成消息，指示PPR完成并且PPR被丢弃，而不在PPR日志中排队PPR。

公开(公告)号：US12182611B2

公开(公告)日：2024-12-31

申请号：US18145457

申请日：2022-12-22

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Philip Ng ,  Anil Kumar

IPC: G06F9/48 ,  G06F9/30 ,  G06F11/07

Abstract: An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.

公开(公告)号：US20240220297A1

公开(公告)日：2024-07-04

申请号：US18090740

申请日：2022-12-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： David Kaplan ,  Jelena Ilic ,  Nippon Raval ,  Philip Ng

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/45545 ,  G06F2009/45579 ,  G06F2009/45587

Abstract: Techniques for implementing programmable control by a guest virtual machine (VM) of interrupts at a processing system using a guest owned backing page are disclosed. The VM programs a guest owned backing page (e.g., a data structure in memory) that designates particular interrupts that are to be blocked. In response to detecting a designated interrupt, system hardware or software blocks the interrupt, rather than executing an interrupt handler to process the interrupt. The VM is thereby able to protect confidential information and program behavior with less risk of a malicious hypervisor failing to protect the VM from, e.g., unexpected or unwanted interrupts, thereby improving overall system security and predictability.

公开(公告)号：US20220188180A1

公开(公告)日：2022-06-16

申请号：US17131512

申请日：2020-12-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Philip Ng ,  Buheng Xu

IPC: G06F11/07 ,  G06F9/46 ,  G06F13/38

Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.