Invention Grant
- Patent Title: Memory devices configured to perform leak checks
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Application No.: US15686754Application Date: 2017-08-25
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Publication No.: US10366767B2Publication Date: 2019-07-30
- Inventor: Jeffrey A. Kessenich , Joemar Sinipete , Chiming Chu , Jason L. Nevill , Kenneth W. Marr , Renato C. Padilla
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/34 ; G11C29/04 ; G01R31/02 ; G11C16/10 ; G11C29/02 ; G11C8/08 ; G11C7/00 ; G11C29/50 ; G11C7/02 ; G11C16/26 ; G11C29/12 ; G11C16/00

Abstract:
Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.
Public/Granted literature
- US20170352431A1 MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS Public/Granted day:2017-12-07
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