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公开(公告)号:US11798622B2
公开(公告)日:2023-10-24
申请号:US17865248
申请日:2022-07-14
CPC分类号: G11C13/0097 , G11C13/0004 , G11C13/004 , G11C13/0033 , G11C13/0069 , G11C2013/0045 , G11C2013/0078
摘要: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.
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公开(公告)号:US20190287634A1
公开(公告)日:2019-09-19
申请号:US16432059
申请日:2019-06-05
发明人: Jeffrey A. Kessenich , Joemar Sinipete , Chiming Chu , Jason L. Nevill , Kenneth W. Marr , Renato C. Padilla
IPC分类号: G11C16/34 , G11C29/50 , G11C7/02 , G11C29/02 , G11C16/26 , G01R31/28 , G11C7/00 , G11C8/08 , G01R31/02 , G11C29/04 , G11C16/10 , G01R31/30
摘要: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.
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公开(公告)号:US09281078B2
公开(公告)日:2016-03-08
申请号:US14302782
申请日:2014-06-12
发明人: Jeffrey A. Kessenich , Joemar Sinipete , Chiming Chu , Jason L. Nevill , Kenneth W. Marr , Renato C. Padilla
IPC分类号: G11C8/08 , G11C7/00 , G11C7/02 , G11C29/02 , G11C29/50 , G11C29/04 , G01R31/02 , G11C16/10 , G11C29/12
CPC分类号: G11C16/3459 , G01R31/02 , G11C7/00 , G11C7/02 , G11C8/08 , G11C16/00 , G11C16/10 , G11C16/26 , G11C16/349 , G11C29/02 , G11C29/025 , G11C29/04 , G11C29/50008 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.
摘要翻译: 操作具有嵌入式泄漏检查的存储器件的方法可以减轻由于存取线缺陷引起的数据丢失事件,并且可以促进改进的功耗特性。 这样的方法可以包括将程序脉冲施加到被选择用于编程的存储器单元的选定访问线,验证所选择的存储单元是否已经达到期望的数据状态,将所选择的访问线路施加到第一电压,将第二电压施加到 未选择的接入线路,将参考电流施加到所选择的接入线路,以及确定所选择的接入线路与未选择接入线路之间的当前流量是否大于参考电流。
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公开(公告)号:US20150364213A1
公开(公告)日:2015-12-17
申请号:US14302782
申请日:2014-06-12
发明人: Jeffrey A. Kessenich , Joemar Sinipete , Chiming Chu , Jason L. Nevill , Kenneth W. Marr , Renato C. Padilla
CPC分类号: G11C16/3459 , G01R31/02 , G11C7/00 , G11C7/02 , G11C8/08 , G11C16/00 , G11C16/10 , G11C16/26 , G11C16/349 , G11C29/02 , G11C29/025 , G11C29/04 , G11C29/50008 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.
摘要翻译: 操作具有嵌入式泄漏检查的存储器件的方法可以减轻由于存取线缺陷引起的数据丢失事件,并且可以促进改进的功耗特性。 这样的方法可以包括将程序脉冲施加到被选择用于编程的存储器单元的选定访问线,验证所选择的存储单元是否已经达到期望的数据状态,将所选择的访问线路施加到第一电压,将第二电压施加到 未选择的接入线路,将参考电流施加到所选择的接入线路,以及确定所选择的接入线路与未选择接入线路之间的当前流量是否大于参考电流。
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公开(公告)号:US20160155513A1
公开(公告)日:2016-06-02
申请号:US15019397
申请日:2016-02-09
发明人: Jeffery A. Kessenich , Joemar Sinipete , Chiming Chu , Jason L. Nevill , Kenneth W. Marr , Renato C. Padilla
CPC分类号: G11C16/3459 , G01R31/02 , G11C7/00 , G11C7/02 , G11C8/08 , G11C16/00 , G11C16/10 , G11C16/26 , G11C16/349 , G11C29/02 , G11C29/025 , G11C29/04 , G11C29/50008 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.
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公开(公告)号:US20240087663A1
公开(公告)日:2024-03-14
申请号:US17944135
申请日:2022-09-13
发明人: William Yu , Daniele Balluchi , Danilo Caraccio , Thomas T. Tangelder , Jacob S. Robertson , James G. Steele , Joemar Sinipete
CPC分类号: G11C29/36 , G11C29/022 , G11C29/42 , G11C2029/3602
摘要: Methods, systems, and devices related to built-in self-test (BIST) circuitry of a controller. The controller can be coupled to multiple memory devices. The BIST circuitry can include registers configured to store burst patterns. The BIST circuitry can perform a BIST operation on the memory devices contemporaneously and using the number of burst patterns.
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公开(公告)号:US20210358546A1
公开(公告)日:2021-11-18
申请号:US15931131
申请日:2020-05-13
IPC分类号: G11C13/00
摘要: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.
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公开(公告)号:US10366767B2
公开(公告)日:2019-07-30
申请号:US15686754
申请日:2017-08-25
发明人: Jeffrey A. Kessenich , Joemar Sinipete , Chiming Chu , Jason L. Nevill , Kenneth W. Marr , Renato C. Padilla
IPC分类号: G11C16/06 , G11C16/34 , G11C29/04 , G01R31/02 , G11C16/10 , G11C29/02 , G11C8/08 , G11C7/00 , G11C29/50 , G11C7/02 , G11C16/26 , G11C29/12 , G11C16/00
摘要: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.
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公开(公告)号:US20170352431A1
公开(公告)日:2017-12-07
申请号:US15686754
申请日:2017-08-25
发明人: Jeffrey A. Kessenich , Joemar Sinipete , Chiming Chu , Jason L. Nevill , Kenneth W. Marr , Renato C. Padilla
IPC分类号: G11C16/34 , G11C7/02 , G11C8/08 , G11C29/50 , G11C29/02 , G01R31/02 , G11C16/26 , G11C29/04 , G11C7/00 , G11C16/10 , G11C29/12 , G11C16/00
CPC分类号: G11C16/3459 , G01R31/02 , G01R31/025 , G01R31/2853 , G01R31/2856 , G01R31/3008 , G11C7/00 , G11C7/02 , G11C8/08 , G11C16/00 , G11C16/10 , G11C16/26 , G11C16/349 , G11C29/02 , G11C29/025 , G11C29/04 , G11C29/50008 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006
摘要: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.
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公开(公告)号:US20220415395A1
公开(公告)日:2022-12-29
申请号:US17865248
申请日:2022-07-14
IPC分类号: G11C13/00
摘要: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.
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