公开(公告)号：US10665307B2

公开(公告)日：2020-05-26

申请号：US16432059

申请日：2019-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/06 ,  G11C16/34 ,  G11C29/04 ,  G01R31/02 ,  G11C16/10 ,  G11C29/02 ,  G11C8/08 ,  G11C7/00 ,  G11C29/50 ,  G11C7/02 ,  G01R31/28 ,  G01R31/30 ,  G11C16/26 ,  G11C29/12 ,  G11C16/00

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.

公开(公告)号：US10366767B2

公开(公告)日：2019-07-30

申请号：US15686754

申请日：2017-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/06 ,  G11C16/34 ,  G11C29/04 ,  G01R31/02 ,  G11C16/10 ,  G11C29/02 ,  G11C8/08 ,  G11C7/00 ,  G11C29/50 ,  G11C7/02 ,  G11C16/26 ,  G11C29/12 ,  G11C16/00

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.

公开(公告)号：US20170352431A1

公开(公告)日：2017-12-07

申请号：US15686754

申请日：2017-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C7/02 ,  G11C8/08 ,  G11C29/50 ,  G11C29/02 ,  G01R31/02 ,  G11C16/26 ,  G11C29/04 ,  G11C7/00 ,  G11C16/10 ,  G11C29/12 ,  G11C16/00

CPC classification number: G11C16/3459 ,  G01R31/02 ,  G01R31/025 ,  G01R31/2853 ,  G01R31/2856 ,  G01R31/3008 ,  G11C7/00 ,  G11C7/02 ,  G11C8/08 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/02 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.

公开(公告)号：US20190287634A1

公开(公告)日：2019-09-19

申请号：US16432059

申请日：2019-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C29/50 ,  G11C7/02 ,  G11C29/02 ,  G11C16/26 ,  G01R31/28 ,  G11C7/00 ,  G11C8/08 ,  G01R31/02 ,  G11C29/04 ,  G11C16/10 ,  G01R31/30

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.

公开(公告)号：US09281078B2

公开(公告)日：2016-03-08

申请号：US14302782

申请日：2014-06-12

Applicant: Micron Technology, Inc.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C8/08 ,  G11C7/00 ,  G11C7/02 ,  G11C29/02 ,  G11C29/50 ,  G11C29/04 ,  G01R31/02 ,  G11C16/10 ,  G11C29/12

CPC classification number: G11C16/3459 ,  G01R31/02 ,  G11C7/00 ,  G11C7/02 ,  G11C8/08 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/02 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

Abstract translation: 操作具有嵌入式泄漏检查的存储器件的方法可以减轻由于存取线缺陷引起的数据丢失事件，并且可以促进改进的功耗特性。 这样的方法可以包括将程序脉冲施加到被选择用于编程的存储器单元的选定访问线，验证所选择的存储单元是否已经达到期望的数据状态，将所选择的访问线路施加到第一电压，将第二电压施加到 未选择的接入线路，将参考电流施加到所选择的接入线路，以及确定所选择的接入线路与未选择接入线路之间的当前流量是否大于参考电流。

公开(公告)号：US20150364213A1

公开(公告)日：2015-12-17

申请号：US14302782

申请日：2014-06-12

Applicant: Micron Technology, Inc.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C29/04 ,  G11C16/10 ,  G01R31/02

CPC classification number: G11C16/3459 ,  G01R31/02 ,  G11C7/00 ,  G11C7/02 ,  G11C8/08 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/02 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

Abstract translation: 操作具有嵌入式泄漏检查的存储器件的方法可以减轻由于存取线缺陷引起的数据丢失事件，并且可以促进改进的功耗特性。 这样的方法可以包括将程序脉冲施加到被选择用于编程的存储器单元的选定访问线，验证所选择的存储单元是否已经达到期望的数据状态，将所选择的访问线路施加到第一电压，将第二电压施加到 未选择的接入线路，将参考电流施加到所选择的接入线路，以及确定所选择的接入线路与未选择接入线路之间的当前流量是否大于参考电流。