Invention Grant
- Patent Title: Face down dual sided chip scale memory package
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Application No.: US16196262Application Date: 2018-11-20
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Publication No.: US10366934B2Publication Date: 2019-07-30
- Inventor: Chan Yoo , Akshay Singh , Yi Xu , Liana Foster , Steven Eskildsen
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Parsons Behle & Latimer
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/31 ; H01L23/00 ; H01L25/065 ; H01L23/48
Abstract:
A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.
Public/Granted literature
- US20190088565A1 Face Down Dual Sided Chip Scale Memory Package Public/Granted day:2019-03-21
Information query
IPC分类:
