INTERCONNECTS FOR A MULTI-DIE PACKAGE
    4.
    发明申请

    公开(公告)号:US20200075548A1

    公开(公告)日:2020-03-05

    申请号:US16120991

    申请日:2018-09-04

    Abstract: Systems, devices, and methods for interconnects for a multi-die package are described. A multi-die package may include a set of conductive pillars and two or more semiconductor dice that each include a bond pad. In some cases, the multi-die package may include a plurality of pillar-wire combinations, and a bond wire may couple a corresponding conductive pillar with a corresponding bond pad. Pillar-wire combinations may each collectively have a matched impedance, or pillar-wire combinations in different groups may have different collective impedances. In other cases, a conductive pillar may be directly coupled with a corresponding bond pad without a bond wire. Different pillar-wire combinations or directly-coupled pillars may carry different signals. In some cases, pillars may be individually impedance-matched to a desired impedance.

    Face down dual sided chip scale memory package

    公开(公告)号:US10366934B2

    公开(公告)日:2019-07-30

    申请号:US16196262

    申请日:2018-11-20

    Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.

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