Invention Grant
- Patent Title: Methods of forming backside self-aligned vias and structures formed thereby
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Application No.: US15754804Application Date: 2015-09-24
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Publication No.: US10367070B2Publication Date: 2019-07-30
- Inventor: Patrick Morrow , Mauro J. Kobrinsky , Kimin Jun , Il-Seok Son , Paul B. Fischer
- Applicant: Intel Corporation , Patrick Morrow , Mauro J. Kobrinsky , Kimin Jun , Il-Seok Son , Paul B. Fischer
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2015/052033 WO 20150924
- International Announcement: WO2017/052562 WO 20170330
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/00 ; H01L29/00 ; H01L29/417 ; H01L21/02 ; H01L21/768 ; H01L21/8234 ; H01L23/522 ; H01L23/528 ; H01L27/088 ; H01L29/08 ; H01L29/10 ; H01L29/165 ; H01L29/66 ; H01L29/78 ; H01L21/84 ; H01L27/12 ; H01L21/265 ; H01L21/306 ; H01L21/324

Abstract:
Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
Public/Granted literature
- US20180248012A1 METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED THEREBY Public/Granted day:2018-08-30
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