- 专利标题： Methods of forming backside self-aligned vias and structures formed thereby
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申请号： US15754804申请日： 2015-09-24
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公开(公告)号： US10367070B2公开(公告)日： 2019-07-30
- 发明人: Patrick Morrow , Mauro J. Kobrinsky , Kimin Jun , Il-Seok Son , Paul B. Fischer
- 申请人： Intel Corporation , Patrick Morrow , Mauro J. Kobrinsky , Kimin Jun , Il-Seok Son , Paul B. Fischer
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Green, Howard & Mughal LLP
- 国际申请： PCT/US2015/052033 WO 20150924
- 国际公布： WO2017/052562 WO 20170330
- 主分类号： H01L21/00
- IPC分类号： H01L21/00 ; H01L27/00 ; H01L29/00 ; H01L29/417 ; H01L21/02 ; H01L21/768 ; H01L21/8234 ; H01L23/522 ; H01L23/528 ; H01L27/088 ; H01L29/08 ; H01L29/10 ; H01L29/165 ; H01L29/66 ; H01L29/78 ; H01L21/84 ; H01L27/12 ; H01L21/265 ; H01L21/306 ; H01L21/324
摘要：
Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
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