Invention Grant
- Patent Title: Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors
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Application No.: US14613876Application Date: 2015-02-04
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Publication No.: US10373956B2Publication Date: 2019-08-06
- Inventor: Rajesh N. Gupta , Farid Nemati , Scott T. Robins
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/74
- IPC: H01L29/74 ; H01L27/102 ; H01L29/73 ; H01L29/735 ; H01L21/02 ; H01L21/8229 ; H01L29/16 ; H01L29/732 ; H01L29/739 ; H01L27/108 ; H01L29/78

Abstract:
Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
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