公开(公告)号：US10914780B2

公开(公告)日：2021-02-09

申请号：US16227348

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Binoy Jose Panakkal ,  Rajesh N. Gupta

IPC: G01R31/26 ,  G05F3/26 ,  G01R19/165 ,  H03F3/50 ,  H03K19/0948

Abstract: A measurement circuit may include a transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to a first reference voltage. The measurement circuit may further include a first operational amplifier including a first input coupled to the second terminal of the transistor and an output coupled to the third terminal of the transistor. The first operational amplifier may further include a second input configured to receive a second reference voltage. The measurement circuit may also include a first unity-gain voltage follower including a second operational amplifier having a first input coupled to the first input of the first operational amplifier. Methods of measuring a threshold voltage, semiconductor devices, and electronic systems are also described.

公开(公告)号：US10242738B2

公开(公告)日：2019-03-26

申请号：US15837896

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Seshadri K. Kolluri ,  Rajesh N. Gupta

IPC: G11C5/06 ,  G11C13/00 ,  G11C11/56

Abstract: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.

公开(公告)号：US10607988B2

公开(公告)日：2020-03-31

申请号：US16398501

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/07 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  H01L27/11553 ,  H01L29/92 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20190296016A1

公开(公告)日：2019-09-26

申请号：US16436689

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

IPC: H01L27/102 ,  H01L21/8229 ,  H01L29/73 ,  H01L29/739 ,  H01L29/16 ,  H01L29/732 ,  H01L21/02 ,  H01L29/735

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

公开(公告)号：US20190259769A1

公开(公告)日：2019-08-22

申请号：US16398501

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  G11C11/408 ,  G11C11/4074 ,  H01L49/02 ,  H01L29/08 ,  H01L27/11582 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/11556

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20190067298A1

公开(公告)日：2019-02-28

申请号：US16043653

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/08 ,  G11C5/14 ,  G11C5/06 ,  G11C11/4074

CPC classification number: H01L27/11273 ,  G11C5/063 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4085 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/10814 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1128 ,  H01L27/11556 ,  H01L27/11582 ,  H01L28/90 ,  H01L29/0847

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US09349737B2

公开(公告)日：2016-05-24

申请号：US14511371

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/105 ,  H01L27/108 ,  G11C11/407

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

公开(公告)号：US20160078917A1

公开(公告)日：2016-03-17

申请号：US14948097

申请日：2015-11-20

Applicant: Micron Technology, Inc.

Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

IPC: G11C11/39

CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

Abstract translation: 一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。 第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。 第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。 第二基极区域在第三结区与第二电极区域相接合。 栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。 一些实施例包括编程晶闸管的方法，并且一些实施例包括形成晶闸管的方法。

公开(公告)号：US20230004307A1

公开(公告)日：2023-01-05

申请号：US17903772

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta

IPC: G06F3/06 ,  G06F12/1009

Abstract: As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.

公开(公告)号：US20200176255A1

公开(公告)日：2020-06-04

申请号：US16208122

申请日：2018-12-03

Applicant: Micron Technology, Inc.

Inventor： Akash Nigam ,  Rajesh N. Gupta

IPC: H01L21/033 ,  H01L21/768

Abstract: A method of forming sublithographic features. The method comprises forming a pattern of lines at a first pitch, the lines comprising horizontal portions and sloped portions. A spacer material is formed adjacent to the lines and portions of the spacer material are removed to form spacers on the lines, the spacers comprising a second pitch. The lines are removed. A sloped profile of the lines prevents the formation of loops of the spacer material, enabling the formation of sublithographic features without using a chop mask or chop mask process acts. Additional methods are disclosed.