Invention Grant
- Patent Title: Read tail latency reduction
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Application No.: US15373450Application Date: 2016-12-08
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Publication No.: US10374634B2Publication Date: 2019-08-06
- Inventor: James N. Malina , Robert L. Horn , Kent Anderson , James C. Alexander , Albert H. Chen
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA Irvine
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA Irvine
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/15

Abstract:
An individual latency indicator is determined for each Data Storage Device (DSD) or memory portion of a DSD storing one or more erasure coded shards generated from an erasure coding on initial data. Each individual latency indicator is associated with a latency in retrieving an erasure coded shard stored in a respective DSD or memory portion. At least one collective latency indicator is determined using determined individual latency indicators, with the at least one collective latency indicator being associated with a latency in retrieving multiple erasure coded shards. The at least one collective latency indicator is compared to a latency limit, and a subset of erasure coded shards is selected to retrieve based on the comparison of the at least one collective latency indicator to the latency limit.
Public/Granted literature
- US20180165015A1 READ TAIL LATENCY REDUCTION Public/Granted day:2018-06-14
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