- 专利标题: High performance phase locked loop
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申请号: US16107822申请日: 2018-08-21
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公开(公告)号: US10374787B2公开(公告)日: 2019-08-06
- 发明人: Armin Tajalli
- 申请人: Kandou Labs, S.A.
- 申请人地址: CH Lausanne
- 专利权人: KANDOU LABS, S.A.
- 当前专利权人: KANDOU LABS, S.A.
- 当前专利权人地址: CH Lausanne
- 代理机构: Invention Mine LLC
- 主分类号: H04L7/00
- IPC分类号: H04L7/00 ; H04L7/033 ; H03K3/356 ; H02M3/07 ; H03K5/26
摘要:
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
公开/授权文献
- US20190007192A1 HIGH PERFORMANCE PHASE LOCKED LOOP 公开/授权日:2019-01-03
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