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公开(公告)号：US11863358B2
公开(公告)日：2024-01-02
申请号：US18049594
申请日：2022-10-25
申请人： Kandou Labs, S.A.
发明人： Ali Hormati , Armin Tajalli , Amin Shokrollahi
CPC分类号： H04L25/03885 , H04L1/0041 , H04L1/0057 , H04L25/03057 , H04L25/03898 , H04L25/49
摘要： Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
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公开(公告)号：US11777475B2
公开(公告)日：2023-10-03
申请号：US17829126
申请日：2022-05-31
申请人： KANDOU LABS, S.A.
CPC分类号： H03K3/0322 , H03B5/24 , H03K2005/00208 , H03L7/0995
摘要： Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.
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公开(公告)号：US11606186B2
公开(公告)日：2023-03-14
申请号：US17684273
申请日：2022-03-01
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
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公开(公告)号：US20230010756A1
公开(公告)日：2023-01-12
申请号：US17813533
申请日：2022-07-19
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： G06F1/3296 , G01R31/30 , G05F1/46 , G06F1/324 , H04L25/02
摘要： Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.
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公开(公告)号：US11018675B2
公开(公告)日：2021-05-25
申请号：US16566648
申请日：2019-09-10
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： H03L7/08 , H03L7/087 , H03L7/099 , H04L7/033 , H04L25/14 , H04L25/02 , H04L25/40 , H04L25/493 , H03K19/21 , H03L7/089 , H04L7/00
摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
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公开(公告)号：US10983587B2
公开(公告)日：2021-04-20
申请号：US16218386
申请日：2018-12-12
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.
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公开(公告)号：US10812298B2
公开(公告)日：2020-10-20
申请号：US16444951
申请日：2019-06-18
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.
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公开(公告)号：US10693688B2
公开(公告)日：2020-06-23
申请号：US16236012
申请日：2018-12-28
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： H04L27/20 , H04L27/148 , H04L27/26 , H04L27/00
摘要： Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.
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9.发明申请公开(公告)号：US20190305991A1
公开(公告)日：2019-10-03
申请号：US16444951
申请日：2019-06-18
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.
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公开(公告)号：US10374787B2
公开(公告)日：2019-08-06
申请号：US16107822
申请日：2018-08-21
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
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