Invention Grant
- Patent Title: Predictive scheduler for memory rank switching
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Application No.: US15382844Application Date: 2016-12-19
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Publication No.: US10379748B2Publication Date: 2019-08-13
- Inventor: James J. Bonanno , Michael J. Cadigan, Jr. , Adam B. Collura , Daniel Lipetz , Patrick J. Meaney , Craig R. Walters
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Dmitry Paskalov
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F13/16 ; G11C11/4074 ; G11C11/406 ; G11C11/409 ; G11C11/4072 ; G11C11/4076 ; G11C5/04 ; G11C11/4091

Abstract:
Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.
Public/Granted literature
- US20180173428A1 PREDICTIVE SCHEDULER FOR MEMORY RANK SWITCHING Public/Granted day:2018-06-21
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