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    Common high and low random bit error correction logic
    3.
    发明授权
    Common high and low random bit error correction logic 有权

    公开(公告)号：US10824504B2

    公开(公告)日：2020-11-03

    申请号：US15953805

    申请日：2018-04-16

    Applicant: International Business Machines Corporation

    Inventor： James A. O'Connor, Jr. ,  Barry M. Trager ,  Warren E. Maule ,  Marc A. Gollub ,  Brad W. Michael ,  Patrick J. Meaney

    IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

    Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

    HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DISTRIBUTED BUFFER MEMORY SYSTEM
    5.
    发明申请
    HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DISTRIBUTED BUFFER MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200073565A1

    公开(公告)日：2020-03-05

    申请号：US16676962

    申请日：2019-11-07

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Susan M. Eickhoff ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

    IPC: G06F3/06

    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

    Dynamically adjustable cyclic redundancy code rates
    6.
    发明授权
    Dynamically adjustable cyclic redundancy code rates 有权

    公开(公告)号：US10530523B2

    公开(公告)日：2020-01-07

    申请号：US15817408

    申请日：2017-11-20

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H04L1/18 ,  H04L1/00 ,  H04L1/20

    Abstract: Aspects of the invention include receiving a specified number of frames of bits at a receiver. At least one of the received frames includes cyclic redundancy code (CRC) bits. The specified number of frames is based at least in part on a CRC rate. It is determined, by performing a CRC check on the received frames, whether a change in transmission errors has occurred in the received frames. An increase in the CRC rate is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred in the received frames. The increase in the CRC rate is synchronized between the receiver and the transmitter; and performed in parallel with functional operations performed by the receiver.

    Reducing uncorrectable errors based on a history of correctable errors
    9.
    发明授权
    Reducing uncorrectable errors based on a history of correctable errors 有权

    公开(公告)号：US10055287B2

    公开(公告)日：2018-08-21

    申请号：US15810722

    申请日：2017-11-13

    Applicant: International Business Machines Corporation

    Inventor： Glenn D. Gilda ,  Patrick J. Meaney

    IPC: G06F11/10 ,  G11C29/52 ,  G11C29/44 ,  G06F11/00

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C29/44 ,  G11C29/52

    Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.

    REDUCING UNCORRECTABLE ERRORS BASED ON A HISTORY OF CORRECTABLE ERRORS
    10.
    发明申请
    REDUCING UNCORRECTABLE ERRORS BASED ON A HISTORY OF CORRECTABLE ERRORS 审中-公开

    公开(公告)号：US20180060167A1

    公开(公告)日：2018-03-01

    申请号：US15810722

    申请日：2017-11-13

    Applicant: International Business Machines Corporation

    Inventor： Glenn D. Gilda ,  Patrick J. Meaney

    IPC: G06F11/10 ,  G11C29/52 ,  G11C29/44

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C29/44 ,  G11C29/52

    Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.

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