Invention Grant
- Patent Title: Method of forming MOS and bipolar transistors
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Application No.: US15897524Application Date: 2018-02-15
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Publication No.: US10381344B2Publication Date: 2019-08-13
- Inventor: Olivier Weber , Emmanuel Richard , Philippe Boivin
- Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
- Applicant Address: FR Crolles FR Rousset FR Paris
- Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics (Rousset) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics (Rousset) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Crolles FR Rousset FR Paris
- Agency: Crowe & Dunlevy
- Priority: FR1652379 20160321
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L21/84 ; H01L27/24 ; H01L21/8249 ; H01L29/732 ; H01L45/00 ; H01L29/417 ; H01L29/66 ; H01L27/12 ; H01L29/08

Abstract:
Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
Public/Granted literature
- US20180175022A1 METHOD OF FORMING MOS AND BIPOLAR TRANSISTORS Public/Granted day:2018-06-21
Information query
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