Invention Grant
- Patent Title: Semiconductor device and method of forming flipchip interconnect structure
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Application No.: US12947414Application Date: 2010-11-16
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Publication No.: US10388626B2Publication Date: 2019-08-20
- Inventor: Rajendra D. Pendse
- Applicant: Rajendra D. Pendse
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/538 ; H05K3/34 ; H05K3/24 ; H01L23/00 ; H01L21/56 ; H01L23/31 ; H05K3/32

Abstract:
A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.
Public/Granted literature
- US20120241945A9 Semiconductor Device and Method of Forming Flipchip Interconnect Structure Public/Granted day:2012-09-27
Information query
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