Invention Grant
- Patent Title: Network-aware cache coherence protocol enhancement
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Application No.: US15358318Application Date: 2016-11-22
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Publication No.: US10402327B2Publication Date: 2019-09-03
- Inventor: David A. Roberts , Ehsan Fatehi
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0815 ; G06F12/084 ; G06F12/0817 ; G06F13/16

Abstract:
A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.
Public/Granted literature
- US20180143905A1 NETWORK-AWARE CACHE COHERENCE PROTOCOL ENHANCEMENT Public/Granted day:2018-05-24
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