Invention Grant
- Patent Title: Power reduction in finFET structures
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Application No.: US15718740Application Date: 2017-09-28
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Publication No.: US10403545B2Publication Date: 2019-09-03
- Inventor: Kuo-Cheng Ching , Chih-Hao Wang , Kuan-Lun Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8234 ; H01L23/535 ; H01L27/088 ; H01L29/06 ; H01L29/08 ; H01L29/66 ; H01L29/10
Abstract:
The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.
Public/Granted literature
- US20190096765A1 POWER REDUCTION IN FINFET STRUCTURES Public/Granted day:2019-03-28
Information query
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