Invention Grant
- Patent Title: Stacked package assembly with voltage reference plane
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Application No.: US15766150Application Date: 2015-11-05
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Publication No.: US10403604B2Publication Date: 2019-09-03
- Inventor: Bok Eng Cheah , Jackson Chung Peng Kong , Ping Ping Ooi , Kooi Chi Ooi , Shanggar Periaman
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/059191 WO 20151105
- International Announcement: WO2017/078717 WO 20170511
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/552 ; H01L23/00 ; H01L25/10 ; H01L25/00 ; H01L21/56 ; H01L23/498 ; H01L23/50

Abstract:
Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
Public/Granted literature
- US20180294252A1 STACKED PACKAGE ASSEMBLY WITH VOLTAGE REFERENCE PLANE Public/Granted day:2018-10-11
Information query
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