公开(公告)号：US10396038B2

公开(公告)日：2019-08-27

申请号：US15505901

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Shanggar Periaman ,  Michael Skinner ,  Yen Hsiang Chew ,  Kheng Tat Mar ,  Ridza Effendi Abd Razak ,  Kooi Chi Ooi

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/495 ,  H01L25/065 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48

Abstract: A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die.

公开(公告)号：US20180145014A1

公开(公告)日：2018-05-24

申请号：US15666448

申请日：2017-08-01

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2924/207

Abstract: An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

公开(公告)号：US09478524B2

公开(公告)日：2016-10-25

申请号：US14852013

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/06183 ,  H01L2224/06189 ,  H01L2224/06517 ,  H01L2224/131 ,  H01L2224/16137 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80894 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Abstract translation: 描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。 在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。 还包括具有半导体管芯的第二基本水平布置的第二MSD结构。 中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。

公开(公告)号：US10403604B2

公开(公告)日：2019-09-03

申请号：US15766150

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Ping Ping Ooi ,  Kooi Chi Ooi ,  Shanggar Periaman

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50

Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.

公开(公告)号：US09812425B2

公开(公告)日：2017-11-07

申请号：US15278532

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/06183 ,  H01L2224/06189 ,  H01L2224/06517 ,  H01L2224/131 ,  H01L2224/16137 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80894 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

公开(公告)号：US09646953B2

公开(公告)日：2017-05-09

申请号：US14775550

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Shanggar Periaman ,  Michael P. Skinner

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  A44B1/00 ,  G06F1/16 ,  H01L25/00 ,  H01L23/48 ,  A45C1/06 ,  B43K29/00 ,  G02C11/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0655 ,  A44B1/00 ,  A45C1/06 ,  B43K29/00 ,  G02C11/10 ,  G06F1/163 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10155 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15158 ,  H01L2924/15192 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161

Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20160327977A1

公开(公告)日：2016-11-10

申请号：US14779300

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jiamiao Tang ,  Junfeng Zhao ,  Michael P. Skinner ,  Yong She ,  Jiun Hann Sir ,  Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

IPC: G06F1/16 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H05K1/18 ,  G06F1/18 ,  H01L23/00 ,  H02J1/14 ,  F03G5/06 ,  A43B3/00 ,  A43B7/14 ,  A41B1/00 ,  A41D1/06 ,  A44C5/00 ,  A44C15/00 ,  A41F9/00 ,  A41D1/08 ,  H01L25/065

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/002 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装。 在实施例中，集成电路（IC）封装可以包括柔性衬底。 柔性基板可以具有与其连接的多个模具。 IC封装可以包括具有第一刚性的第一封装材料，其设置在柔性基板上以至少部分地封装多个裸片的每个裸片。 IC封装还可包括设置在柔性基板上的具有第二刚性的第二封装材料。 在实施例中，第二刚性和第一刚度彼此不同。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09778688B2

公开(公告)日：2017-10-03

申请号：US14779300

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jiamiao Tang ,  Junfeng Zhao ,  Michael P. Skinner ,  Yong She ,  Jiun Hann Sir ,  Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

IPC: H01L23/48 ,  G06F1/16 ,  H01L23/31 ,  A41B1/00 ,  A41D1/06 ,  A41D1/08 ,  A41F9/00 ,  A43B3/00 ,  A43B7/14 ,  A44C5/00 ,  A44C15/00 ,  F03G5/06 ,  G06F1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H02J1/14 ,  H05K1/18

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/002 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

公开(公告)号：US20160343686A1

公开(公告)日：2016-11-24

申请号：US14775550

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Shanggar Periaman ,  Michael P. Skinner

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  A44B1/00 ,  G06F1/16 ,  H01L25/00 ,  G02C11/00 ,  A45C1/06 ,  B43K29/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0655 ,  A44B1/00 ,  A45C1/06 ,  B43K29/00 ,  G02C11/10 ,  G06F1/163 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10155 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15158 ,  H01L2924/15192 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161

Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于小尺寸或可佩戴装置的集成电路（IC）封装技术和配置。 在一个实施例中，装置可以包括具有第一侧和与第一侧相对设置的第二侧和设置在第一侧和第二侧之间的侧壁的衬底，侧壁限定衬底的周边，以及多个 布置在基板的第一侧和第二侧之间的贯通基板通孔（TSV）以及布置在第一侧上的第一介电层，并且包括电路径特征以将一个或多个管芯的电信号路由在第一 电介质层。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150201497A1

公开(公告)日：2015-07-16

申请号：US14665730

申请日：2015-03-23

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/36 ,  H05K3/10 ,  H05K3/34 ,  H01L23/13 ,  H05K1/11

CPC classification number: H05K1/185 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19106 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/183 ,  H05K3/10 ,  H05K3/34 ,  H05K3/36 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.

Abstract translation: 一种装置包括无芯安装基板和设置在无芯安装基板上的插入件，其具有设置在插入件中的凹部中的芯片和无芯基板。 该装置可以包括与插入器中的互连通道接触的封装间焊料凸块，以及包括顶部封装衬底和设置在顶部封装衬底上的顶部管芯的顶部芯片封装。 顶部封装衬底与封装间焊料凸块接触。