公开(公告)号：US11798894B2

公开(公告)日：2023-10-24

申请号：US16451557

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Kooi Chi Ooi ,  Min Suet Lim

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2924/3025

Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 μm pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

公开(公告)号：US11758662B2

公开(公告)日：2023-09-12

申请号：US17828142

申请日：2022-05-31

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H05K1/14 ,  H01R12/77 ,  H05K1/02 ,  H05K1/18 ,  H05K3/36 ,  H05K3/30

CPC classification number: H05K1/147 ,  H01R12/77 ,  H05K1/028 ,  H05K1/181 ,  H05K3/303 ,  H05K3/361 ,  H05K2201/055 ,  H05K2201/2018 ,  H05K2203/166

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.

公开(公告)号：US11527485B2

公开(公告)日：2022-12-13

申请号：US17088618

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/00

Abstract: The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.

公开(公告)号：US11527463B2

公开(公告)日：2022-12-13

申请号：US16984173

申请日：2020-08-04

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/522

Abstract: According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.

公开(公告)号：US20220369460A1

公开(公告)日：2022-11-17

申请号：US17828142

申请日：2022-05-31

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H05K1/14 ,  H01R12/77 ,  H05K1/02 ,  H05K1/18 ,  H05K3/36 ,  H05K3/30

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.

公开(公告)号：US11375617B2

公开(公告)日：2022-06-28

申请号：US16887902

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H05K1/00 ,  H05K1/14 ,  H01R12/77 ,  H05K1/02 ,  H05K1/18 ,  H05K3/36 ,  H05K3/30

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.

公开(公告)号：US20220102295A1

公开(公告)日：2022-03-31

申请号：US17498089

申请日：2021-10-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/498

Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

公开(公告)号：US20210375735A1

公开(公告)日：2021-12-02

申请号：US16984173

申请日：2020-08-04

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L23/522 ,  H01L21/48

Abstract: According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.

公开(公告)号：US20210184326A1

公开(公告)日：2021-06-17

申请号：US17030634

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Ling Li Ong ,  Kin Wai Lee ,  Bok Eng Cheah ,  Yang Liang Poh ,  Yean Ling Soon

IPC: H01P3/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/552

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include an assembly having asymmetrically situated conductors. In selected examples, the assembly includes a ground plane, a central shield portion, a first side shield portion on a. first side, a second side shield portion on a second side, a first conductor asymmetrically situated between the central shield portion and the first side shield portion, a second conductor asymmetrically situated between the central shield portion and the second side shield portion, and dielectric within the assembly.

公开(公告)号：US11037874B2

公开(公告)日：2021-06-15

申请号：US16450287

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/552 ,  H01L23/528 ,  H01L23/00

Abstract: An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads.