Invention Grant
- Patent Title: Prevention of subchannel leakage current in a semiconductor device with a fin structure
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Application No.: US15525183Application Date: 2014-12-22
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Publication No.: US10403752B2Publication Date: 2019-09-03
- Inventor: Karthik Jambunathan , Glenn A. Glass , Chandra S. Mohapatra , Anand S. Murthy , Stephen M. Cea , Tahir Ghani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/US2014/071841 WO 20141222
- International Announcement: WO2016/105336 WO 20160630
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/66
Abstract:
An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and lll-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.
Public/Granted literature
- US20170330966A1 PREVENTION OF SUBCHANNEL LEAKAGE CURRENT Public/Granted day:2017-11-16
Information query
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