公开(公告)号：US12057491B2

公开(公告)日：2024-08-06

申请号：US16239090

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Dax M. Crum ,  Stephen M. Cea ,  Leonard P. Guler ,  Tahir Ghani

IPC: H01L27/12 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6653 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7853

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

公开(公告)号：US20230275085A1

公开(公告)日：2023-08-31

申请号：US17682037

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Sukru Yemenicioglu ,  Mohit K. Haran ,  Shengsi Liu ,  Robert Joachim ,  Dan S. Lavric ,  Stephen M. Cea

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/41775

Abstract: Techniques are provided herein to form an integrated circuit having a grid of gate cut structures such that a gate cut structure exists between pairs of semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. Each of the gate cut structures may be formed at the same time in a grid-like pattern across the integrated circuit (or a portion thereof). Sidewall spacer structures on the sidewalls of the gate structure wrap around ends of each gate structure to form a given gate cut structure.

公开(公告)号：US11276691B2

公开(公告)日：2022-03-15

申请号：US16134824

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.

公开(公告)号：US20220059656A1

公开(公告)日：2022-02-24

申请号：US17453088

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US11195919B2

公开(公告)日：2021-12-07

申请号：US16148621

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/04 ,  H01L29/165 ,  H01L27/12 ,  H01L27/092

Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US20210343710A1

公开(公告)日：2021-11-04

申请号：US17372345

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow ,  Stephen M. Cea

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L29/78

Abstract: Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.

公开(公告)号：US10790281B2

公开(公告)日：2020-09-29

申请号：US15773325

申请日：2015-12-03

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Roza Kotlyar ,  Stephen M. Cea ,  Patrick H. Keys

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/06 ,  H01L29/78 ,  H01L21/822 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

公开(公告)号：US20200161298A1

公开(公告)日：2020-05-21

申请号：US16615378

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow ,  Stephen M. Cea

IPC: H01L27/088 ,  H01L27/06 ,  H01L23/532 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8234

Abstract: Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.

公开(公告)号：US20200052117A1

公开(公告)日：2020-02-13

申请号：US16605312

申请日：2017-05-15

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/786

Abstract: Disclosed herein are structures and techniques for device isolation in integrated circuit (IC) assemblies. In some embodiments, an IC assembly may include multiple transistors spaced apart by an isolation region. The isolation region may include a doped semiconductor body whose dopant concentration is greatest at one or more surfaces, or may include a material that is lattice-mismatched with material of the transistors, for example.

公开(公告)号：US10468489B2

公开(公告)日：2019-11-05

申请号：US15747719

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Uygar E. Avci ,  David L. Kencke ,  Patrick Morrow ,  Kerryann Foley ,  Stephen M. Cea ,  Rishabh Mehandru

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.