Invention Grant
- Patent Title: Guard ring design enabling in-line testing of silicon bridges for semiconductor packages
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Application No.: US15749465Application Date: 2015-10-29
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Publication No.: US10418312B2Publication Date: 2019-09-17
- Inventor: Arnab Sarkar , Sujit Sharan , Dae-Woo Kim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/058072 WO 20151029
- International Announcement: WO2017/074391 WO 20170504
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/544 ; H01L21/66 ; H01L23/58 ; H01L25/065 ; H01L23/00 ; H01L25/18

Abstract:
Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.
Public/Granted literature
- US20180226331A1 GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES Public/Granted day:2018-08-09
Information query
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