公开(公告)号：US12142553B2

公开(公告)日：2024-11-12

申请号：US18138512

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US11322445B2

公开(公告)日：2022-05-03

申请号：US16319647

申请日：2016-09-12

Applicant: Intel Corporation

Inventor： Yidnekachew S. Mekonnen ,  Dae-Woo Kim ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/34 ,  H01L23/48 ,  H01L21/44 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.

公开(公告)号：US11257743B2

公开(公告)日：2022-02-22

申请号：US16542248

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US11094633B2

公开(公告)日：2021-08-17

申请号：US16305758

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim ,  Jackie C. Preciado

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

公开(公告)号：US10177083B2

公开(公告)日：2019-01-08

申请号：US15749462

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L23/48

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

公开(公告)号：US20180366438A1

公开(公告)日：2018-12-20

申请号：US15781998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Ravindranath V. Mahajan

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00

Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.

公开(公告)号：US12243812B2

公开(公告)日：2025-03-04

申请号：US18386913

申请日：2023-11-03

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

公开(公告)号：US11784150B2

公开(公告)日：2023-10-10

申请号：US17825739

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/3512

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

公开(公告)号：US11626372B2

公开(公告)日：2023-04-11

申请号：US17143142

申请日：2021-01-06

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

IPC: H01L23/538 ,  H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US10916514B2

公开(公告)日：2021-02-09

申请号：US16576520

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

IPC: H01L23/538 ,  H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.