Invention Grant
- Patent Title: Master/slave frequency locked loop
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Application No.: US15850593Application Date: 2017-12-21
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Publication No.: US10425089B2Publication Date: 2019-09-24
- Inventor: Stephen V. Kosonocky , Mikhail Rodionov , Joyce C. Wong
- Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Zagorin Cave LLP
- Main IPC: H03L7/099
- IPC: H03L7/099 ; G06F1/08 ; H03K5/00 ; H03B1/04 ; H03K3/037

Abstract:
A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
Public/Granted literature
- US20190199363A1 MASTER/SLAVE FREQUENCY LOCKED LOOP Public/Granted day:2019-06-27
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