Invention Grant
- Patent Title: Memory subsystem I/O performance based on in-system empirical testing
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Application No.: US15372031Application Date: 2016-12-07
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Publication No.: US10446222B2Publication Date: 2019-10-15
- Inventor: Theodore Z. Schoenborn , Christopher P. Mozak
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G11C11/4093 ; G11C29/56 ; G11C29/06 ; G11C11/4074 ; G11C11/4076 ; G11C11/4096 ; G11C29/04

Abstract:
A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.
Public/Granted literature
- US20170213585A1 MEMORY SUBSYSTEM I/O PERFORMANCE BASED ON IN-SYSTEM EMPIRICAL TESTING Public/Granted day:2017-07-27
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