A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.