公开(公告)号：US20190287965A1

公开(公告)日：2019-09-19

申请号：US16422199

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78 ,  H01L27/118 ,  H01L23/528

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US10347627B2

公开(公告)日：2019-07-09

申请号：US15926572

申请日：2018-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/08 ,  H01L27/11 ,  H01L23/52 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11504

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US10930648B2

公开(公告)日：2021-02-23

申请号：US16422199

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/11 ,  H01L23/52 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L23/528 ,  H01L27/118 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11504 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L29/417

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US09245771B2

公开(公告)日：2016-01-26

申请号：US14264120

申请日：2014-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Keum-Hee Ma ,  In-Young Lee ,  Moon Gi Cho ,  Chajea Jo ,  Taeje Cho

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L21/561 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/92 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L21/568 ,  H01L21/78 ,  H01L2224/1191 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.

Abstract translation: 提供了具有通过电极的半导体封装及其制造方法。 该方法可以包括提供包括第一电路层的第一衬底，在第一衬底的前表面上形成前模层，研磨第一衬底的后表面，形成穿透第一衬底的第一贯穿电极以电 连接到第一电路层，在第一衬底的背表面上提供第二衬底，第二衬底包括电连接到第一贯通电极的第二电路层，在第一衬底的后表面上形成后模层 衬底，封装第二衬底的后模层，以及去除前模层。

公开(公告)号：US10211089B2

公开(公告)日：2019-02-19

申请号：US15619648

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Gi Cho ,  Byungju Kang ,  Janie Hyojin Kim

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L21/02

Abstract: A semiconductor device and a fabricating method thereof are provided. The method includes sequentially forming an interlayer insulating layer and a hard mask layer on a substrate with first and second regions, performing a first patterning process on the hard mask layer to form first openings in the first and second regions, performing a second patterning process on the hard mask layer to form second openings in the first and second regions, and performing a third patterning process on the hard mask layer to selectively form at least one third opening in only the second region. The third patterning process includes forming a first photoresist pattern with openings on the hard mask layer, and the opening of the first photoresist pattern on the first region is overlapped with the second opening on the first region, when viewed in a plan view.

公开(公告)号：US10453838B2

公开(公告)日：2019-10-22

申请号：US15689418

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan Jun ,  Deokhan Bae ,  HeonJong Shin ,  Jaeran Jang ,  Moon Gi Cho ,  YoungWoo Cho

IPC: H01L27/06 ,  H01L23/522 ,  H01L29/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3213 ,  H01L23/532

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

公开(公告)号：US20180366463A1

公开(公告)日：2018-12-20

申请号：US15926572

申请日：2018-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53295 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11504 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11807 ,  H01L29/0646 ,  H01L29/785 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US20210167063A1

公开(公告)日：2021-06-03

申请号：US17170252

申请日：2021-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L29/78

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US20190252372A1

公开(公告)日：2019-08-15

申请号：US16395593

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan Jun ,  Deokhan Bae ,  HeonJong Shin ,  Jaeran Jang ,  Moon Gi Cho ,  YoungWoo Cho

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.