公开(公告)号：US20240030345A1

公开(公告)日：2024-01-25

申请号：US18112312

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong Shin ,  Seon-Bae Kim ,  Jaeran Jang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/78391 ,  H01L29/66545 ,  H01L29/0847 ,  H01L29/6656

Abstract: In some embodiments, the semiconductor device includes a substrate comprising a cell region, a dummy region spaced apart from the cell region in a first direction, and a border region between the cell region and the dummy region, an active pattern on the cell region, a device isolation layer on the substrate, source/drain patterns on the active pattern and channel patterns between the source/drain patterns, cell gate electrodes crossing the channel patterns in a second direction, active contacts disposed on the cell region and between the cell gate electrodes and coupled to the source/drain patterns, dummy gate electrodes on the dummy region and on the device isolation layer, dummy contacts on the dummy region and on a side surface of each of the dummy gate electrodes, an interlayer insulating layer on the side surface of each of the dummy gate electrodes, and a dam structure on the border region.

公开(公告)号：US20190252372A1

公开(公告)日：2019-08-15

申请号：US16395593

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan Jun ,  Deokhan Bae ,  HeonJong Shin ,  Jaeran Jang ,  Moon Gi Cho ,  YoungWoo Cho

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

公开(公告)号：US20240421216A1

公开(公告)日：2024-12-19

申请号：US18676858

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggyu Han ,  Heonjong Shin ,  Juneyoung Park ,  Sanghee Lee ,  Jaeran Jang ,  Mingi Chung

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: An integrated circuit semiconductor device includes a base layer including a first surface and a second surface, a gate structure on the first surface of the base layer, a first source and drain region on a side of the gate structure, a second source and drain region on another side of the gate structure, a first placeholder in the base layer in a lower portion of the first source and drain region and electrically connected to the first source and drain region, a second placeholder in the base layer in a lower portion of the second source and drain region, and a metal power rail on the first placeholder and the second placeholder on the second surface of the base layer and electrically connected to the first placeholder.

公开(公告)号：US20160365274A1

公开(公告)日：2016-12-15

申请号：US15145924

申请日：2016-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Jaeran Jang ,  Yoonhae Kim

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/16 ,  H01L27/11 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L21/76825 ,  H01L21/31155 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅极图案，形成间隔物以覆盖栅极图案的两个侧壁，形成层间绝缘层以覆盖栅极图案和间隔物，并形成穿透层间绝缘层的接触孔 并暴露间隔物的侧壁。 间隔件的形成包括形成间隔层以覆盖栅极图案并将硅离子注入间隔层。 间隔层是介电常数低于氧化硅的介电常数的氮化物基低k绝缘层。

公开(公告)号：US10002788B2

公开(公告)日：2018-06-19

申请号：US15145924

申请日：2016-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Jaeran Jang ,  Yoonhae Kim

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/11 ,  H01L21/3115 ,  H01L29/165

CPC classification number: H01L21/76825 ,  H01L21/31155 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.

公开(公告)号：US20240258228A1

公开(公告)日：2024-08-01

申请号：US18541630

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juneyoung Park ,  Heonjong Shin ,  Jaeran Jang ,  Doohyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/16137 ,  H01L2224/16227 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/19041

Abstract: An integrated circuit device includes a first substrate having a first surface and a second surface opposite to the first surface, and including an active device therein, BEOL structure disposed on the first surface of the first substrate and configured to route signals, a second substrate disposed on the first surface of the first substrate with the first BEOL structure disposed therebetween, and including a passive device therein, a power distribution structure disposed on the second surface of the first substrate, a first bonding structure positioned on the first BEOL structure, and a second bonding structure disposed between the first bonding structure and the second substrate.

公开(公告)号：US10453838B2

公开(公告)日：2019-10-22

申请号：US15689418

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan Jun ,  Deokhan Bae ,  HeonJong Shin ,  Jaeran Jang ,  Moon Gi Cho ,  YoungWoo Cho

IPC: H01L27/06 ,  H01L23/522 ,  H01L29/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3213 ,  H01L23/532

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.