公开(公告)号：US11538913B2

公开(公告)日：2022-12-27

申请号：US17175850

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan Hwang ,  Heonjong Shin ,  Sunghun Jung ,  Doohyun Lee ,  Hwichan Jun ,  Hakyoon Ahn

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/285 ,  H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

公开(公告)号：US10522537B2

公开(公告)日：2019-12-31

申请号：US15937093

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhwa Kim ,  Kyungin Choi ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/768 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/311

Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

公开(公告)号：US20230369317A1

公开(公告)日：2023-11-16

申请号：US18356545

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US11742345B2

公开(公告)日：2023-08-29

申请号：US17866066

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan Hwang ,  Hwichan Jun

IPC: H01L21/822 ,  H01L27/085 ,  H01L21/8234

CPC classification number: H01L27/085 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823481

Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

公开(公告)号：US20220231013A1

公开(公告)日：2022-07-21

申请号：US17223829

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US20220157815A1

公开(公告)日：2022-05-19

申请号：US17152388

申请日：2021-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device having a self-aligned gate structure includes: providing at least one channel structure above at least one substrate; depositing at least one gate masking layer on the at least one channel structure so that the at least one gate masking layer is formed on top and side surfaces of the at least one channel structure and spread outward above the at least one substrate to form outer-extended portions of the at least one gate masking layer, before a gate-cut process is performed, wherein the at least one gate masking layer is self-aligned with respect to the at least one channel structure by the depositing; and removing the outer-extended portions of the at least one gate masking layer so that the at least one gate masking layer at both sides of the at least one channel structure has a same width.

公开(公告)号：US20190252372A1

公开(公告)日：2019-08-15

申请号：US16395593

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan Jun ,  Deokhan Bae ,  HeonJong Shin ,  Jaeran Jang ,  Moon Gi Cho ,  YoungWoo Cho

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

公开(公告)号：US11935922B2

公开(公告)日：2024-03-19

申请号：US17970777

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang Ill Seo ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US11502167B2

公开(公告)日：2022-11-15

申请号：US17146136

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Kang Ill Seo ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US10199471B2

公开(公告)日：2019-02-05

申请号：US15059519

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok Choi ,  Hwichan Jun ,  Yoonhae Kim ,  Chulsung Kim ,  Heungsik Park ,  Doo-Young Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.