Invention Grant
- Patent Title: Transistor with dual spacer and forming method thereof
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Application No.: US15846150Application Date: 2017-12-18
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Publication No.: US10453938B2Publication Date: 2019-10-22
- Inventor: Chia-Ling Wang , Ping-Hung Chiang , Chang-Po Hsiung , Chia-Wen Lu , Nien-Chung Li , Wen-Fang Lee , Chih-Chung Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN201711146633 20171117
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/088 ; H01L29/08 ; H01L29/78 ; H01L21/311 ; H01L21/8234 ; H01L29/423 ; H01L29/06

Abstract:
A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.
Public/Granted literature
- US20190157418A1 TRANSISTOR WITH DUAL SPACER AND FORMING METHOD THEREOF Public/Granted day:2019-05-23
Information query
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