- Patent Title: Switching reduction bus using data bit inversion with shield lines
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Application No.: US15703736Application Date: 2017-09-13
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Publication No.: US10459871B2Publication Date: 2019-10-29
- Inventor: Akinori Funahashi , Chikara Kondo
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F13/12
- IPC: G06F13/12 ; G06F13/42 ; G11C8/18 ; G11C5/06 ; G06F13/16 ; G11C7/02 ; G11C7/10
Abstract:
Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.
Public/Granted literature
- US20190079893A1 SWITCHING REDUCTION BUS USING DATA BIT INVERSION WITH SHIELD LINES Public/Granted day:2019-03-14
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