Invention Grant
- Patent Title: Substrate with embedded stacked through-silicon via die
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Application No.: US13757153Application Date: 2013-02-01
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Publication No.: US10461032B2Publication Date: 2019-10-29
- Inventor: Javier Soto Gonzalez , Houssam Jomaa
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/538 ; H01L21/56 ; H01L23/498 ; H01L23/00 ; H01L21/683 ; H01L25/065 ; H01L25/10 ; H01L25/00 ; H01L23/14

Abstract:
A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
Public/Granted literature
- US20130147043A1 SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE Public/Granted day:2013-06-13
Information query
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