公开(公告)号：US10461032B2

公开(公告)日：2019-10-29

申请号：US13757153

申请日：2013-02-01

Applicant: Intel Corporation

Inventor： Javier Soto Gonzalez ,  Houssam Jomaa

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/14

Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

公开(公告)号：US11107766B2

公开(公告)日：2021-08-31

申请号：US16575117

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Javier Soto Gonzalez ,  Houssam Jomaa

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L25/00 ,  H01L23/31 ,  H01L23/14

Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

公开(公告)号：US20240112999A1

公开(公告)日：2024-04-04

申请号：US17955689

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Houssam Jomaa ,  Dilan Seneviratne ,  Whitney Bryks ,  Srinivas Venkata Ramanuja Pietambaram ,  Kristof Darmawikarta

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49894

Abstract: An electronic system comprising can have a substrate with a core layer formed from at least one layer of glass. The glass layers can each be stacked with a dielectric material disposed between each layer of glass. The glass layers can be prepatterned before assembly of the layered glass core system.

公开(公告)号：US09040842B2

公开(公告)日：2015-05-26

申请号：US13867851

申请日：2013-04-22

Applicant: Intel Corporation

Inventor： Ravi Nalla ,  Omar Bchir ,  Houssam Jomaa

IPC: H01L23/00 ,  H05K3/38 ,  H05K3/46 ,  H05K1/02 ,  H05K3/18

CPC classification number: H01L23/53238 ,  C08J5/18 ,  C08J2363/00 ,  H01L24/26 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0298 ,  H05K3/181 ,  H05K3/381 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2203/0773 ,  H05K2203/0796 ,  Y10T156/1052 ,  Y10T428/249921 ,  Y10T428/254 ,  Y10T428/268 ,  H01L2924/00

Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施方案中，提出了铜金属化与具有部分固化的环氧树脂填料的电介质的改进的机械粘附。 在这方面，引入具有环氧树脂材料和多个环氧微球的衬底累积膜，其中微球的内部未完全固化。 还公开并要求保护其他实施例。